1. Field of the Invention
The present invention relates to electrically erasable programmable read only memory (EEPROM) devices and in particular to an improved EEPROM structure which requires less substrate surface area and is simpler to manufacture than prior art EEPROMs.
2. Description of the Prior Art
The most recent generation of memories is the EEPROM, which allows its programmed contents to be electrically erased, thereby allowing reprogramming. Unlike typical erasable programmable read only memories (EPROMs), which are usually erased in bulk by exposure to ultra-violet light, an EEPROM allows electrical erasure, typically within ten milliseconds.
A typical prior art EEPROM is described by Tickle, U.S. Pat. No. 4,377,857, issued Mar. 22, 1983. A typical prior art EEPROM memory cell is shown in FIG. 1a and includes transistor 100 having source 101 and drain 102 formed in silicon substrate 99, source 101 and drain 102 being of a conductivity type opposite to that of substrate 99, and having channel region 103 formed therebetween. Gate insulation 104 electrically insulates polycrystalline silicon floating gate 105 from channel 103 and drain 102. A very thin tunnel oxide region 106 electrically insulates a small portion of floating gate 105 from drain 102. This prior art structure further includes control gate 108, and insulation layer 107 formed between floating gate 105 and control gate 108.
Also shown in FIG. 1a are the various capacitances which inherently form in the cell: capacitance C.sub.ch is the capacitance formed between floating gate 105 and channel region 103; capacitance C.sub.pp is the capacitance formed between control gate 108 and floating gate 105; and capacitance C.sub.t is the capacitance formed between floating gate 105 and drain 102.
Shown in FIG. 1b is a schematic circuit diagram of a prior art EEPROM which uses transistor 100, shown in FIG. 1a, and word coupling transistor 200. Control gate (CG) 108, word line (WL) 205, bit line (BL) 210, connections to substrate 99, and source 101 and drain 102 of transistor 100 are shown. Word line 205 is connected to the control gate of transistor 200. Described below is the operation of such a prior art EEPROM.
Table 1 shows the various voltages applied to the circuit of FIG. 1b.
TABLE 1 ______________________________________ WL BL CG Source Substrate ______________________________________ Read V.sub.cc V.sub.sense V.sub.r ground ground Write V.sub.pp ground V.sub.pp ground ground Erase V.sub.pp V.sub.pp ground float ground ______________________________________
In order to store a logical 0 in the EEPROM, electrons are injected into floating gate 105 to provide a negative voltage on floating gate 105, thus increasing the control gate threshold voltage needed to turn on transistor 100. This injection of electrons on floating gate 105 is accomplished, for example, by Fowler-Nordheim tunneling. One technique to achieve this electron tunneling is to place high voltage V.sub.pp (typically 15-20 volts) on control gate 108, grounding drain 102 by applying high voltage V.sub.pp to word line 205 and grounding bit line 210, and grounding source 101 and substrate 99. This causes electrons to tunnel from drain region 102, through tunneling oxide 106, to floating gate 105, which is capacitively coupled to control gate 108. After this programming of the cell to a 34 logical 0, sufficient electrons are stored within floating gate 105 to increase control gate threshold voltage V.sub.t of transistor 100 (typically to greater than 5 volts) such that transistor 100 will not turn on in response to read voltage V.sub.r applied to control gate 108.
Reading of the state of transistor 100 is accomplished by applying operating voltage V.sub.cc (typically five volts) to voltage V.sub.sense (typically V.sub.cc /2) to bit line 210, applying read voltage V.sub.r to control gate 108, and grounding source 101 of transistor 100. If a logical 0 is stored in the EEPROM (i.e., floating gate 105 is negatively charged) transistor 100 will not turn on in response to read voltage V.sub.r, and no current flows between bit line 210 and source 101 of transistor 100, indicating a logical 0.
In order to erase the EEPROM or, in other words, to change the state of the EEPROM from a logical 0 to a logical 1, floating gate 105 is discharged. This is accomplished, for example, by placing control gate 108 at ground, applying high positive voltage V.sub.pp to drain 102 (typically 20 volts) by applying a high voltage to word line 205 and bit line 210, disconnecting source 101 (i.e., source 101 is "floating"), and connecting substrate 99 to ground. This causes electrons to flow from floating gate 105, through tunnel oxide 106, to drain 102, thereby discharging floating gate 105. Discharging floating gate 105 decreases control gate threshold voltage V.sub.t, and stores a logical 0 in the memory cell. Applying read voltage V.sub.r to control gate 108 will turn on transistor 100 and current will flow between bit line 210 and source 101 of transistor 100, indicating a logical 1.
Using the structure of FIG. 1a and the circuit of FIG. 1b, programming can also be accomplished by storing a positive charge on floating gate 105. This is done by drawing free electrons from floating gate 105, through tunnel oxide 106, and into drain 102. Erasing is accomplished by drawing electrons back through tunnel oxide 106 from drain 102 and into floating gate 105. Using this method, reading of the cell does not require a voltage to control gate 108 since transistor 100 is already on if floating gate 105 is positively charged (indicating a logical 1) and off if floating gate 105 has no charge (indicating a logical 0). The various voltage levels are shown in Table 2.
TABLE 2 ______________________________________ WL BL CG Source Substrate ______________________________________ Read V.sub.cc V.sub.sense ground ground ground Write V.sub.pp V.sub.pp ground float ground Erase V.sub.pp ground V.sub.pp ground ground ______________________________________
The speed of charging floating gate 105 (i.e., programming the cell) and discharging floating gate (i.e., erasing the cell) is determined by the magnitude of the electric field across tunnel oxide 106. This in turn is dependent on the magnitude of voltage V.sub.pp, which is applied between control gate 108 and drain 102, as well as the coupling ratio of the cell. Coupling ratio defines what portion of the applied voltage V.sub.pp appears across tunnel oxide 106 between floating gate 105 and drain 102. For the EEPROM shown in FIG. 1, the voltage V.sub.f between floating gate 105 and drain 102, during programming, may be expressed as a fraction of the programming voltage V.sub.pp as follows: ##EQU1## where PCR is the programming coupling ratio. During erasing, control gate 108 and substrate 99 are grounded, and the voltage V.sub.f between floating gate 105 and drain 102 during erasing may be expressed as follows: ##EQU2## where ECR is the erasing coupling ratio.
Since it is desirable to provide an EEPROM cell having high programming and erasing speeds, it is desirable to construct the cell such that the programming and erasing coupling ratios are as close to unity as possible. To accomplish this, the value of capacitance C.sub.t should be made as small as possible, capacitance C.sub.pp should be as large as possible, and capacitance C.sub.ch should be small during programming and large during erasing. Capacitance is calculated using the equation: EQU C=AK.epsilon..sub.0 /t, where
C is the capacitance PA1 .epsilon..sub.0 is the permittivity of empty space (8.85.times.10.sup.-2 coul.sup.2 /newton.sup.2 -m.sup.2) PA1 K is the dielectric constant (3.9 for SiO.sub.2) PA1 A is the plate area, and PA1 t is the dielectric thickness.
Limiting factors in reducing C.sub.t are that present technology is only capable of producing plate areas down to a minimum of 1 micron.sup.2, and that the thickness of tunnel oxide 106 must be made sufficiently small to allow efficient tunneling to occur between floating gate 105 and drain 102. Capacitance C.sub.pp can be increased without limit by reducing dielectric thickness or increasing plate area, thus aiding the efficiency of the cell, however, achieving a consistent thin dielectric thickness over a large area is difficult, and maintaining a small cell size is critical. In the prior art, C.sub.ch is not alterable between programming and erasing operations. Thus, there is a tradeoff to be made between reduced cell size versus increased programming and erasing efficiencies. Furthermore, increasing the programming and erasing voltage V.sub.pp will increase the speed of programming and erasing the EEPROM cell. However, it is also highly desirable to minimize the programming and erasing voltage V.sub.pp to prevent circuit failure due to undesired voltage breakdowns, as well as to avoid the generation of V.sub.pp to be unduly burdensome.
Also, manufacturing of prior art EEPROMs involves the relatively complex and time consuming process of forming two separate gates: the floating gate and control gate. Any teaching to eliminate the control gate would reduce cell size, by eliminating contact electrode area, and ease manufacturing complexity and cost. Some prior art EEPROMs, such as that described by R. Cuppens et al. in the article, "An EEPROM for Microprocessors and Custom Logic", IEEE Journal of Solid-State Circuits, Vol. SC-20, No. 2, April 1985, and described by J. Miyamoto et al. in the article, "An Experimental 5-V-Only 256-Kbit CMOS EEPROM with a High Performance Single-Polysilicon Cell", IEEE Journal of Solid-State Circuits, Vol. SC-21, No. 5, October 1986, use a single layer of polycrystalline silicon (poly-Si) to act as a floating gate and use an N+diffused area to act as a control gate, which is capacitively coupled to the poly-Si layer. This, however, requires extra substrate surface to form the N+ diffused control gate region.
Finally, prior art devices require the word line transistor, such as that shown in FIG. 1b as transistor 200, to operate quickly so reading can be accomplished quickly. Since these word line transistors must be sufficiently large to handle the high programming and erasing voltages, the word line transistors cannot be freely reduced in size for increased speed for reading. One way to decrease the reaction time of the cell is to increase the width of the sense transistor channel. However, this increase in channel width increases capacitance between the floating gate and the substrate, thus, decreasing coupling ratio, and also increases the cell area.
What would be desirable in the industry would be an EEPROM which is simple to manufacture, relatively inexpensive, may be programmed and erased using a lower voltage than prior art EEPROMS, can be read extremely fast, and uses up less chip surface area.